Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed to prevent loss of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device's end-use requirements, and the programmed data can be stored for a long period of time.
Non-volatile memory cells generally include a charge-trapping layer structure situated between a control gate and a substrate having a source and a drain region. Often the charge-trapping structure is constructed of multiple layers, for example, a first insulating layer disposed on the substrate, a charge-trapping layer disposed on the first insulating layer, and a second insulating layer disposed on the charge-trapping layer beneath the gate electrode. Charge-trapping layers may be of a type which hold charge in a localized manner, or they may comprise floating gates which are comprised of a conductive material such that the stored charge is spread throughout the floating gate layer. Charge-trapping layers which store charge in a localized manner, such as silicon nitride, are capable of storing more than one area of charge per memory cell. Such localized charge storage allows one charge (bit-1) to be stored in the charge-trapping layer in an area adjacent to one source/drain region and another charge (bit-2) to be stored in the charge-trapping layer in an area adjacent to the other source/drain region. Two-bit memory cells have received a great deal of attention in recent years as demands for reduced memory cell size and increased memory capacity have grown.
Unfortunately, non-volatile memory cells which employ charge-trapping layers and store charge in a localized manner are not without problems. For example, in nitride storage memory cells where the charge-trapping layer generally comprises a silicon nitride layer sandwiched between two silicon dioxide layers (“ONO structure”), hydrogen atoms may become trapped at the interfacial sites between the silicon substrate and the bottom oxide (first insulating) layer of the charge-storage ONO structure. It is believed that interfacially trapped hydrogen is at least partly responsible for some loss of threshold voltage in memory devices having an interface between silicon and another material.
In addition, source/drain regions in memory devices are often formed as a series of parallel lines of buried-diffusion doped implants (i.e., bit lines) beneath the surface of the substrate. The formation of bit lines in a substrate, for example, by ion implantation, can damage other layers of material (e.g., a silicon dioxide dielectric layer) which have already been deposited on the substrate and may also damage the substrate/oxide layer interface. Such damage to these additional layers is believed to also cause data storage and other performance problems in memory devices.
Accordingly, there is a need for improved methods of forming non-volatile memory cells and devices which employ localized charge-trapping layers.